There are at least three standard methods of packaging multi-chip power modules. One popular method incorporates direct bonded copper (DBC) substrates that comprise a ceramic tile with copper bonded to top and/or bottom sides of the ceramic tile. Alumina (Al2O3), aluminum nitride (AlN), and beryllium oxide (BeO) are materials that are usable as the ceramic tile. DBC substrates are known for their high thermal conductivity and excellent electrical isolation. DBC substrates comprising AlN and copper have a thermal conductivity of at least 150 Watts per meter Kelvin (W/mK). However, DBC substrates have disadvantages of high cost, large design rules, and a limitation of only one electrical conductor routing layer.
Another multi-chip packaging method utilizes leadframe technology with either DBC isolation or a cascode-stacked die technique. However, present leadframe technology not well suited for multiple die structures that are coplanar. In particular, present leadframe technology can be compromised thermally and/or mechanically when attempted to be used for coplanar multi-chip structures.
Yet another standard multi-chip packaging technology incorporates laminate printed circuit board (PCB) technology. An advantage of laminate PCB technology is low cost, integration flexibility, and electrical conductor routing. However, a significant disadvantage of PCB technology is low thermal performance if there are multiple dies requiring high power dissipation that cannot utilize electrically conducting thermal vias due to unequal electrical potentials on both sides of the vias.
What is needed is an integrated power module with improved electrical isolation and improved thermal conductivity that is structured to realize the advantages of each of the above multi-chip packaging methods while avoiding the discussed limitations of those methods.